Microchip Technology /ATSAMV71J20 /MATRIX /SCFG[5]

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Interpret as SCFG[5]

DEFMSTR_TYPE=NONE

Description

Slave Configuration Register 0

Fields

SLOT_CYCLE	Maximum Bus Grant Duration for Masters
DEFMSTR_TYPE	Default Master Type 0 (NONE): No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1 (LAST): Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 2 (FIXED): Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
FIXED_DEFMSTR	Fixed Default Master

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